GATE CS 2024 Set 1 — Question 28

MSQ+1 / -0MediumCombinational HazardsCombinational CircuitsDigital Logic

Digital Logic → Combinational Circuits → Combinational Hazards

Last updated 20 August 2026

Question

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?

A logic circuit with input $X$ branching into an AND gate directly and through a NOT gate. The output is $Y$.

With no propagation delays, the output

Y

is always logic Zero

With no propagation delays, the output

Y

is always logic One

With propagation delays, the output

Y

can have a transient logic One after

X

transitions from logic Zero to logic One

With propagation delays, the output

Y

can have a transient logic Zero after

X

transitions from logic One to logic Zero

Correct answer

(A) With no propagation delays, the output Y is always logic Zero; (C) With propagation delays, the output Y can have a transient logic One after X transitions from logic Zero to logic One

Solution

The circuit implements the Boolean function

Y = X \cdot \overline{X}

1.No propagation delays: In an ideal scenario without delays, the output is the logical product of a variable and its complement, which is always 0. Thus,

Y = X \cdot \overline{X} = 0

for any value of

X

. Statement (A) is correct.

2.With propagation delays: Let the propagation delay of the NOT gate be

\Delta t

. The output of the AND gate at time

t

Y(t) = X(t) \cdot \overline{X(t - \Delta t)}

Transition $X: 0 \to 1$ : Suppose $X$ changes from 0 to 1 at $t = 0$ . For the interval $0 < t < \Delta t$ , the direct input to the AND gate is 1, while the output of the NOT gate remains 1 because the change in $X$ hasn't propagated through it yet. Consequently, $Y = 1 \cdot 1 = 1$ for a duration of $\Delta t$ . This is known as a transient logic One or a static-0 hazard. Statement (C) is correct.
Transition $X: 1 \to 0$ : Suppose $X$ changes from 1 to 0 at $t = 0$ . For $0 < t < \Delta t$ , the direct input to the AND gate becomes 0 immediately, while the output of the NOT gate is still 0. Thus, $Y = 0 \cdot 0 = 0$ . No transient occurs.

Since the steady-state output is always 0, the circuit cannot have a transient logic Zero (which would require a

1 \to 0 \to 1

transition). Therefore, statement (B) is incorrect, and statement (D) is incorrect.

GATE CS 2024 Set 1 — Question 28

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