GATE EC 2016 Set 1 — Question 26
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Communications → Analog Communications → FM/PM Demodulation & PLL
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Question
The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by- counter (comprising outputs) is sketched below. The synthesizer is excited with a signal (Input 1). The free-running frequency of the PLL is set to . Assume that the commutator switch makes contacts repeatedly in the order 1-2-3-4.
Correct answer
(A) 10 kHz, 20 kHz, 40 kHz, 80 kHz
Solution
In a Phase Locked Loop (PLL) frequency synthesizer, when the loop is in lock, the frequency at the input of the phase detector from the feedback path must equal the reference frequency ().
Given .
The feedback path contains a divide-by- counter, so .
In lock condition: .
The commutator switch selects in the order 1-2-3-4:
Given .
The feedback path contains a divide-by- counter, so .
In lock condition: .
The commutator switch selects in the order 1-2-3-4:
1.For position 1, .
2.For position 2, .
3.For position 3, .
4.For position 4, .
Thus, the synthesized frequencies are .Continue learning with Success Tracker
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