GATE CS 2014 Set 3 — Question 55
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Digital Logic → Sequential Circuits → Counters (Sync, Async)
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Question
The above synchronous sequential circuit built using JK flip-flops is initialized with . The state sequence for this circuit for the next 3 clock cycles is
Correct answer
(C) 100, 110, 111
Solution
Reading the connections from the circuit:
So the next three states are .
- FF2: ,
- FF1: ,
- FF0: ,
| Present | Next | |||
|---|---|---|---|---|
| 000 | 10 (set) | 01 (reset) | 01 (reset) | 100 |
| 100 | 10 (set) | 10 (set) | 01 (reset) | 110 |
| 110 | 00 (hold) | 10 (set) | 11 (toggle) | 111 |
- (A) 001, 010, 011 – wrong: the first clock sets , not .
- (B) 111, 110, 101 – wrong: from 000, and are reset, not set.
- (C) 100, 110, 111 – correct.
- (D) 100, 011, 001 – wrong: from 100, stays 1 because .
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