60 solved GATE CS questions on Digital Logic, drawn from 9 exam years and grouped by year. Every question shows the official answer and a step-by-step solution.
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Separate combinational output (determined by present inputs) from sequential output (determined by present inputs and stored state). These selected foundations connect Boolean algebra, gate-level design, and finite-state machines. Verify each simplification by evaluating a few input combinations.
Our study notes and original examples support the PYQs below; they are not official exam questions or a replacement for the current syllabus.
Every Boolean function over n variables can be expressed as a sum of minterms or product of maxterms. Karnaugh maps group adjacent cells sharing a common literal; each group of 2^k cells eliminates k variables. Verify that the simplified expression matches the original truth table.
Check yourself: Does every minterm in the original function belong to at least one group?
A multiplexer selects one of 2^n data inputs using n select lines. A decoder maps an n-bit input to one of 2^n output lines. Propagation delay determines the time between input change and stable output; hazards are transient glitches during this window.
Check yourself: Are the select and enable signals correctly connected?
Two's complement represents signed integers: the most significant bit has a negative weight. For n bits, the range is −2^(n−1) to 2^(n−1) − 1. Overflow occurs when the result exceeds this range, not merely when a carry exists.
Check yourself: Does the sign bit of the result correctly reflect the operands' signs?
A D flip-flop samples its input at the active clock edge and holds the value until the next edge. Setup time is the minimum duration the input must be stable before the edge; hold time is the minimum after. Violating either can cause metastability.
Check yourself: Is the data stable for the required setup window before the clock edge?
A Mealy machine's output depends on current state and input; a Moore machine's output depends only on current state. State transition tables or diagrams must account for every state-input pair. Unreachable states can be removed; equivalent states can be merged.
Check yourself: Have you assigned an output for every state (Moore) or every state-input pair (Mealy)?
Original teaching example · not a PYQ
Original mini-example: simplify the Boolean function F(A, B, C) = Σm(0, 1, 2, 5, 7) using a Karnaugh map.
F = A'B' + AC + A'C'.
In 4-bit two's complement, what decimal value does 1101 represent?
−3.
The sign bit contributes −8. The remaining bits contribute 4 + 0 + 1 = 5. Total: −8 + 5 = −3. Alternatively, invert to 0010, add 1 to get 0011 = 3, negate to −3.
Supplemental reading, not an official GATE reading list or an endorsement of these notes.
Free supplemental course covering combinational and sequential logic, finite state machines, and digital system design with lecture notes and problem sets.
This page shows 60 recent questions from the released archive, newest first. For older questions and complete papers, browse all GATE CS papers. Questions can carry more than one subject tag; counts are not marks weightage.
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