GATE CS 2015 Set 1 — Question 53
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Digital Logic → Sequential Circuits → Counters (Sync, Async)
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Question
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
Correct answer
(A) 0110110...
Solution
Let be the output of the D flip-flop and be the output of the JK flip-flop.
Connections:
Connections:
- Inputs before edge: (Toggle), .
- New outputs: toggles . becomes .
- State: . Sequence: 0, 1.
- Inputs before edge: (Hold), .
- New outputs: holds . becomes .
- State: . Sequence: 0, 1, 1.
- Inputs before edge: (Toggle), .
- New outputs: toggles . becomes .
- State: . Sequence: 0, 1, 1, 0.
- Inputs before edge: (Toggle), .
- New outputs: toggles . becomes .
- State: . Sequence: 0, 1, 1, 0, 1.
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