GATE CS 2015 Set 2 — Question 65

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NAT+2 / -0MediumAdders & SubtractorsCombinational CircuitsDigital Logic

Digital Logic → Combinational Circuits → Adders & Subtractors

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Question

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ___________.
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