GATE CS 2015 Set 3 — Question 50
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Programming & Data Structures → Arrays & Strings → Array Operations (1D, 2D)
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Question
Consider the following two C code segments. Y and X are one and two dimensional arrays of size and respectively, where . Assume that in both code segments, elements of Y are initialized to 0 and each element X[i][j] of array X is initialized to i+j. Further assume that when stored in main memory all elements of X are in same main memory page frame.Code segment 1:
Code Segment 2:
Which of the following statements is/are correct?S1: Final contents of array Y will be same in both code segments
S2: Elements of array X accessed inside the for loop shown in code segment 1 are contiguous in main memory
S3: Elements of array X accessed inside the for loop shown in code segment 2 are contiguous in main memory
//initialize elements of Y to 0
//initialize elements X[i][j] of X to i+j
for(i = 0; i < n; i++)
Y[i] += X[0][i];
//initialize elements of Y to 0
//initialize elements X[i][j] of X to i+j
for(i = 0; i < n; i++)
Y[i] += X[i][0];
S2: Elements of array X accessed inside the for loop shown in code segment 1 are contiguous in main memory
S3: Elements of array X accessed inside the for loop shown in code segment 2 are contiguous in main memory
Correct answer
(C) Only S1 and S2 are correct
Solution
Let's analyze the dependencies:S1: Anti-dependence between and
- : MUL R7, R1, R3 (Reads R1, R3; Writes R7)
- : MUL R7, R8, R9 (Reads R8, R9; Writes R7)
- Anti-dependence (WAR) occurs if reads a register that later writes. Here, reads {R1, R3} and writes {R7}. No intersection.
- Both write to R7, which is an Output Dependence (WAW), not Anti-dependence. So S1 is False.
- : MUL R7, R1, R3 (Reads R1, R3)
- : ADD R3, R2, R4 (Writes R3)
- reads R3, and subsequently writes to R3. This is a Write-After-Read (WAR) dependency, also known as anti-dependence. So S2 is True.
- In a typical in-order pipeline, instructions are fetched and operands are read (e.g., in ID stage) in order. reads R3 before reaches the Write Back (WB) stage. Thus, the read happens before the overwrite, naturally satisfying the dependency without stalls. Stalls are usually required for RAW (Read-After-Write) hazards, not WAR, unless in specific out-of-order scenarios without renaming. The statement "always creates one or more stalls" is too strong and generally False for standard pipelines.
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