GATE CS 2015 Set 3 — Question 49
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Computer Organization & Architecture → Instruction Pipelining → Data Hazards (RAW, WAR, WAW)
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Question
Consider the following code sequence having five instructions to . Each of these instructions has the following format.OP Ri, Rj, Rkwhere operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri.
: ADD R1, R2, R3
: MUL R7, R1, R3
: SUB R4, R1, R5
: ADD R3, R2, R4
: MUL R7, R8, R9Consider the following three statements.S1: There is an anti-dependence between instructions and
S2: There is an anti-dependence between instructions and
S3: Within an instruction pipeline an anti-dependence always creates one or more stallsWhich one of above statements is/are correct?
: ADD R1, R2, R3
: MUL R7, R1, R3
: SUB R4, R1, R5
: ADD R3, R2, R4
: MUL R7, R8, R9Consider the following three statements.S1: There is an anti-dependence between instructions and
S2: There is an anti-dependence between instructions and
S3: Within an instruction pipeline an anti-dependence always creates one or more stallsWhich one of above statements is/are correct?
Correct answer
(B) Only S2 is true
Solution
Let's analyze the dependencies:
- Anti-dependence (WAR - Write After Read): Occurs when an instruction writes to a register that a previous instruction reads. The write must not happen before the read.
- : MUL R7, R1, R3 (Reads R1, R3; Writes R7)
- : MUL R7, R8, R9 (Reads R8, R9; Writes R7)
- Both write to R7. This is an Output Dependence (WAW), not anti-dependence. S1 is False.
- : MUL R7, R1, R3 (Reads R3)
- : ADD R3, R2, R4 (Writes R3)
- reads R3 and writes R3. Since comes before , this is an Anti-dependence (WAR). S2 is True.
- Anti-dependencies (WAR) typically do not cause stalls in a standard 5-stage pipeline because the read (in ID stage) happens before the write (in WB stage) of the subsequent instruction. Even if stages are different, register renaming or simple pipeline timing usually resolves WAR without stalls. It does not always create stalls. S3 is False.
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