GATE CS 2017 Set 1 — Question 33
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Digital Logic → Sequential Circuits → Flip-Flops (JK, T, D)
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Question
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.
Initially, both and are set to 1 (before the clock cycle). The outputs
Correct answer
(B) Q₁ Q₀ after the 3^(rd) cycle are 11 and after the 4^(th) cycle are 01 respectively
Solution
From the circuit diagram:
State: Cycle 2:
State: Cycle 3:
State: (This matches the initial state)Cycle 4:
State: Result:
After 3rd cycle:
After 4th cycle:
- The input to the D flip-flop () is . So, .
- The input to the T flip-flop () is . So, .
State: Cycle 2:
State: Cycle 3:
State: (This matches the initial state)Cycle 4:
State: Result:
After 3rd cycle:
After 4th cycle:
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