GATE CS 2017 Set 1 — Question 9
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Digital Logic → Combinational Circuits → Adders & Subtractors
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Question
When two 8-bit numbers and in 2's complement representation (with and as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are and the carry bits are . An overflow is said to have occurred if
Correct answer
(C) (A₇ · B₇ · S₇ + A₇ · B₇ · S₇) is 1
Solution
In 2's complement addition, overflow occurs when the result of adding two numbers with the same sign yields a result with the opposite sign.Let and be the sign bits of the operands, and be the sign bit of the sum.
.Alternatively, overflow is defined as for the MSB, i.e., , but the expression in option (C) is the standard logic expression derived from the sign bits.
1.Positive + Positive = Negative: If and , but , overflow has occurred. This condition is represented as .
2.Negative + Negative = Positive: If and , but , overflow has occurred. This condition is represented as .
Combining these two cases, overflow occurs if:.Alternatively, overflow is defined as for the MSB, i.e., , but the expression in option (C) is the standard logic expression derived from the sign bits.
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