GATE CS 2021 Set 1 — Question 38

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MCQ+2 / -0.67MediumCounters (Sync, Async)Sequential CircuitsDigital LogicFlip-Flops (JK, T, D)

Digital Logic → Sequential Circuits → Counters (Sync, Async)

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Question

Consider a 3-bit counter, designed using T flip-flops, as shown below:
Circuit diagram of a 3-bit counter with three T flip-flops (T_P, T_Q, T_R) driven by a common clock pulse. Output R is fed back to input T_P, P' drives T_Q, and Q' drives T_R.
Assuming the initial state of the counter given by PQR as 000, what are the next three states?
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