GATE EE 2014 Set 3 — Question 62
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Analog & Digital Electronics → Digital Logic Circuits → Comparator & Schmitt Trigger
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Question
A hysteresis type TTL inverter is used to realize an oscillator in the circuit shown in the figure.
If the lower and upper trigger level voltages are V and V, the period (in ms), for which output is LOW, is __________.
Correct answer
0.62 to 0.66
Solution
In a relaxation oscillator using a hysteresis inverter, the output is LOW when the capacitor is discharging from the upper threshold voltage () to the lower threshold voltage ().The discharge equation for the capacitor voltage is:Assuming the output LOW voltage V:At , the capacitor voltage reaches the lower threshold :Given from the circuit and problem statement:
Calculating the time constant:Calculating :The period for which the output is LOW is approximately ms.
Calculating the time constant:Calculating :The period for which the output is LOW is approximately ms.
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