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GATE EE Analog & Digital Electronics Previous Year Questions

60 solved GATE EE questions on Analog & Digital Electronics, drawn from 10 exam years and grouped by year. Every question shows the official answer and a step-by-step solution.

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Revision companion

Analog & Digital Electronics: bias first, then analyse the signal path

Establish the DC operating point before applying small-signal models. For digital circuits, define the truth table or state diagram before drawing gates or flip-flops. These selected foundations connect semiconductor device circuits, op-amp configurations, and combinational and sequential logic through original exercises.

Our study notes and original examples support the PYQs below; they are not official exam questions or a replacement for the current syllabus.

Before you start

  • Kirchhoff's laws, voltage dividers, and the concept of a piecewise-linear device model.
  • Binary number representation, basic Boolean operations (AND, OR, NOT), and truth tables.

Concepts to revise before solving

Diode circuits

An ideal diode conducts with zero forward voltage drop and blocks reverse current. In a practical model, include the forward voltage V_D (about 0.7 V for silicon). Half-wave and full-wave rectifiers convert AC to pulsating DC; a smoothing capacitor reduces ripple. Clipping and clamping circuits shift or limit voltage waveforms.

Check yourself: Have you verified the assumed diode state (on or off) with the resulting circuit voltages?

BJT and MOSFET biasing and small-signal models

A BJT in the active region satisfies I_C = β I_B, and its small-signal transconductance is g_m = I_C/V_T. A MOSFET in saturation has I_D = (k_n/2)(V_GS − V_th)² and g_m = 2I_D/(V_GS − V_th). Establish the Q-point before computing voltage gain using the small-signal model.

Check yourself: Is the transistor in the active (BJT) or saturation (MOSFET) region at the bias point?

Operational amplifier circuits

An ideal op-amp has infinite open-loop gain, infinite input impedance, and zero output impedance. With negative feedback: the inverting amplifier gain is −R_f/R_1; the non-inverting gain is 1 + R_f/R_1. Virtual short (V+ = V−) and virtual open (no input current) simplify analysis. Without negative feedback, the output saturates.

Check yourself: Is the op-amp in the linear region (negative feedback present) or saturated?

Boolean algebra and combinational logic

Every Boolean function can be expressed as a sum of minterms or a product of maxterms. Karnaugh maps group adjacent cells to eliminate variables: a group of 2^k cells eliminates k variables. Multiplexers, decoders, and encoders implement common combinational functions. Verify simplification by checking all input combinations.

Check yourself: Does every minterm of the original function belong to at least one group?

Sequential logic: flip-flops and counters

A D flip-flop samples its input at the active clock edge. A T flip-flop toggles when T = 1. An n-bit binary counter has 2^n states and wraps to zero after reaching 2^n − 1. Synchronous counters change all bits simultaneously; ripple counters propagate changes sequentially, accumulating delay.

Check yourself: Does the counter's modulus match the total number of distinct states?

Mistakes to avoid

Applying the small-signal model without first establishing a valid DC bias point.
Solve the DC circuit with all AC sources set to zero. Confirm the transistor is in the correct operating region before using g_m or r_π.
Using virtual-short analysis when the op-amp lacks negative feedback.
Without negative feedback the op-amp output rails to the supply. Virtual short applies only when negative feedback forces V+ ≈ V−.
Grouping non-adjacent cells in a Karnaugh map.
Adjacent cells differ in exactly one variable. The map wraps at edges; verify adjacency before grouping.

Original teaching example · not a PYQ

Work through the reasoning

Original mini-example: an ideal op-amp inverting amplifier has R₁ = 10 kΩ (input resistor) and R_f = 47 kΩ (feedback resistor). The non-inverting input is grounded. If the input voltage is V_in = 0.5 V DC, find the output voltage, voltage gain, and the current through R₁.

  1. Virtual ground: V⁻ = V⁺ = 0 V. Current through R₁: I = (V_in − 0)/R₁ = 0.5/10000 = 50 µA.
  2. No current enters the ideal op-amp input, so the same 50 µA flows through R_f from the virtual ground toward the output.
  3. V_out = 0 − I × R_f = −50 × 10⁻⁶ × 47000 = −2.35 V.
  4. Voltage gain A_v = V_out/V_in = −2.35/0.5 = −4.7, which equals −R_f/R₁ = −47/10.

V_out = −2.35 V; voltage gain = −4.7; current through R₁ = 50 µA.

Try it before reading the answer

A 3-bit binary up-counter starts at state 000. After 10 clock pulses, what is the counter's output state?

Show answer and reasoning

010 (decimal 2).

A 3-bit counter has 2³ = 8 states (000 through 111) and wraps to 000 after 111. After 10 pulses: 10 mod 8 = 2, so the counter is at 010. Equivalently, it completes one full cycle (8 pulses) and then counts 2 more.

Go deeper with free learning resources

Supplemental reading, not an official GATE reading list or an endorsement of these notes.

Apply this to the previous-year questions

Previous-year questions by year

This page shows 60 recent questions from the released archive, newest first. For older questions and complete papers, browse all GATE EE papers. Questions can carry more than one subject tag; counts are not marks weightage.

GATE EE 20265 questions

  1. Set 1 Q33In the linear regulator circuit shown, the base to emitter voltage VBEV_{BE} of the BJT is 0.6 V0.6\text{ V}. The Zener diode clamps the base voltage to…NAT · +1 marks · Medium
  2. Set 1 Q37In the circuit shown, the open loop gain of the operational amplifier is A0=105A_0 = 105. What is the voltage gain of the circuit? (Round off to two decimal…MCQ · +2 marks · Medium
  3. Set 1 Q45The digital circuit shown has 3 inputs (xx, yy, and zz). The simplified logical expression for the output (OUT) is:MCQ · +2 marks · Medium
  4. Set 1 Q46The MOSFET switches shown in the circuit are ideal. [figure] Which of the following is the correct option for Boolean logical expression of the output (OUT),…MCQ · +2 marks · Medium
  5. Set 1 Q61Consider the circuit shown. Assume that the diode (DD) is ideal. Given vs=100sin⁡(2π50t)v_s = 100 \sin(2\pi 50t) V, Vdc=50V_{dc} = 50 V, and R=10ΩR = 10 \Omega, the average value…NAT · +2 marks · Medium

GATE EE 20255 questions

  1. Set 1 Q16Which one of the following statements is true about the small signal voltage gain of a MOSFET based single stage amplifier?MCQ · +1 marks · Easy
  2. Set 1 Q17Assuming ideal op-amps, the circuit represents a [figure]MCQ · +1 marks · Medium
  3. Set 1 Q37A Boolean function is given as…MCQ · +2 marks · Medium
  4. Set 1 Q38In the circuit, IDCI_{DC} is an ideal current source. The transistors M1M_1 and M2M_2 are assumed to be biased in saturation, wherein VinV_{in} is the input…MCQ · +2 marks · Hard
  5. Set 1 Q56The op-amps in the following circuit are ideal. The voltage gain of the circuit is ____ (round off to the nearest integer). [figure]NAT · +2 marks · Medium

GATE EE 20246 questions

  1. Set 1 Q24Simplified form of the Boolean function F(P,Q,R,S)=PˉQˉ+PˉQS+PQˉRˉSˉ+PQˉRSˉF(P, Q, R, S) = \bar{P}\bar{Q} + \bar{P}QS + P\bar{Q}\bar{R}\bar{S} + P\bar{Q}R\bar{S} isMCQ · +1 marks · Medium
  2. Set 1 Q25In the circuit, the present value of ZZ is 1. Neglecting the delay in the combinatorial circuit, the values of SS and ZZ, respectively, after the…MCQ · +1 marks · Easy
  3. Set 1 Q26To obtain the Boolean function F(X,Y)=XYˉ+XˉF(X, Y) = X\bar{Y} + \bar{X}, the inputs PQRSPQRS in the figure should be [figure]MCQ · +1 marks · Easy
  4. Set 1 Q42A BJT biasing circuit is shown in the figure, where VBE=0.7V_{BE} = 0.7 V and β=100\beta = 100. The Quiescent Point values of VCEV_{CE} and ICI_C are respectively…MCQ · +2 marks · Medium
  5. Set 1 Q60In the given circuit, the diodes are ideal. The current II through the diode D1D1 in milliamperes is ___________ (rounded off to two decimal places). [figure]NAT · +2 marks · Medium
  6. Set 1 Q61A difference amplifier is shown in the figure. Assume the op-amp to be ideal. The CMRR (in dB) of the difference amplifier is _________ (rounded off to 2…NAT · +2 marks · Hard

GATE EE 20236 questions

  1. Set 1 Q37Consider the OP AMP based circuit shown in the figure. Ignore the conduction drops of diodes D1D_1 and D2D_2. All the components are ideal and the breakdown…MCQ · +2 marks · Medium
  2. Set 1 Q40An 8 bit ADC converts analog voltage in the range of 0 to +5 V+5\text{ V} to the corresponding digital code as per the conversion characteristics shown in…MCQ · +2 marks · Medium
  3. Set 1 Q44All the elements in the circuit shown in the following figure are ideal. Which of the following statements is/are true? [figure]MSQ · +2 marks · Hard
  4. Set 1 Q56Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states,…NAT · +2 marks · Hard
  5. Set 1 Q57In a given 8-bit general purpose micro-controller there are following flags. C-Carry, A-Auxiliary Carry, O-Overflow flag, P-Parity (0 for even, 1 for odd) R0…NAT · +2 marks · Medium
  6. Set 1 Q59The Zener diode in circuit has a breakdown voltage of 5 V. The current gain β\beta of the transistor in the active region in 99. Ignore base-emitter voltage…NAT · +2 marks · Medium

GATE EE 20227 questions

  1. Set 1 Q12For an ideal MOSFET biased in saturation, the magnitude of the small signal current gain for a common drain amplifier isMCQ · +1 marks · Easy
  2. Set 1 Q16The steady state output (VoutV_{out}), of the circuit shown below, will [figure]MCQ · +1 marks · Medium
  3. Set 1 Q25For the circuit shown below with ideal diodes, the output will be [figure]MCQ · +1 marks · Easy
  4. Set 1 Q26A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)NAT · +1 marks · Easy
  5. Set 1 Q29The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propagation delay of 20 ns20\text{ ns}, is…NAT · +1 marks · Medium
  6. Set 1 Q36The output impedance of a non-ideal operational amplifier is denoted by ZoutZ_{out}. The variation in the magnitude of ZoutZ_{out} with increasing frequency, f, in…MCQ · +2 marks · Hard
  7. Set 1 Q44The current gain (Iout/IinI_{out}/I_{in}) in the circuit with an ideal current amplifier given below is [figure]MCQ · +2 marks · Medium

GATE EE 20216 questions

  1. Set 1 Q32A 16-bit synchronous binary up-counter is clocked with a frequency fCLKf_{CLK}. The two most significant bits are OR-ed together to form an output YY.…NAT · +1 marks · Medium
  2. Set 1 Q33In the BJT circuit shown, beta of the PNP transistor is 100. Assume VBE=−0.7V_{BE} = -0.7 V. The voltage across RCR_C will be 55 V when R2R_2 is ______ kΩ\Omega.…NAT · +1 marks · Medium
  3. Set 1 Q34In the circuit shown, the input ViV_i is a sinusoidal AC voltage having an RMS value of 230230 V ±20%\pm 20\%. The worst-case peak-inverse voltage seen across any…NAT · +1 marks · Medium
  4. Set 1 Q35In the circuit shown, a 5 V5\text{ V} Zener diode is used to regulate the voltage across load R0R_0. The input is an unregulated DC voltage with a minimum value…NAT · +1 marks · Medium
  5. Set 1 Q47A counter is constructed with three D flip-flops. The input-output pairs are named (D0,Q0)(D_0, Q_0), (D1,Q1)(D_1, Q_1), and (D2,Q2)(D_2, Q_2), where the subscript 0 denotes…MCQ · +2 marks · Medium
  6. Set 1 Q62A CMOS Schmitt-trigger inverter has a low output level of 0 V0\text{ V} and a high output level of 5 V5\text{ V}. It has input thresholds of 1.6 V1.6\text{ V} and…NAT · +2 marks · Hard

GATE EE 20206 questions

  1. Set 1 Q25A common-source amplifier with a drain resistance, RD=4.7 kΩR_D = 4.7 \text{ k}\Omega, is powered using a 10 V power supply. Assuming that the transconductance,…MCQ · +1 marks · Easy
  2. Set 1 Q40Consider the diode circuit shown below. The diode, DD, obeys the current-voltage characteristic…MCQ · +2 marks · Medium
  3. Set 1 Q41A non-ideal diode is biased with a voltage of −0.03-0.03 V, and a diode current of I1I_1 is measured. The thermal voltage is 2626 mV and the ideality factor for…MCQ · +2 marks · Medium
  4. Set 1 Q62A non-ideal Si-based pn junction diode is tested by sweeping the bias applied across its terminals from −5 V-5\text{ V} to +5 V+5\text{ V}. The effective thermal…NAT · +2 marks · Hard
  5. Set 1 Q63The temperature of the coolant oil bath for a transformer is monitored using the circuit shown. It contains a thermistor with a temperature-dependent…NAT · +2 marks · Hard
  6. Set 1 Q64An 8085 microprocessor accesses two memory locations (2001H) and (2002H), that contain 8-bit numbers 98H and B1H, respectively. The following program is…NAT · +2 marks · Medium

GATE EE 20196 questions

  1. Set 1 Q26Given, VgsV_{gs} is the gate-source voltage, VdsV_{ds} is the drain source voltage, and VthV_{th} is the threshold voltage of an enhancement type NMOS transistor,…MCQ · +1 marks · Easy
  2. Set 1 Q27A current controlled current source (CCCS) has an input impedance of 10 Ω10\ \Omega and output impedance of 100 kΩ100\ \text{k}\Omega. When this CCCS is used in a…MCQ · +1 marks · Medium
  3. Set 1 Q43The enhancement type MOSFET in the circuit below operates according to the square law. μnCox=100μA/V2\mu_n C_{ox} = 100 \mu A/V^2, the threshold voltage (VTV_T) is…MCQ · +2 marks · Medium
  4. Set 1 Q44In the circuit below, the operational amplifier is ideal. If V1=10 mVV_1 = 10\text{ mV} and V2=50 mVV_2 = 50\text{ mV}, the output voltage (VoutV_{\text{out}}) is [figure]MCQ · +2 marks · Medium
  5. Set 1 Q45The output expression for the Karnaugh map shown below is [figure]MCQ · +2 marks · Easy
  6. Set 1 Q46In the circuit shown below, XX and YY are digital inputs, and ZZ is a digital output. The equivalent circuit is a [figure]MCQ · +2 marks · Easy

GATE EE 20185 questions

  1. Set 1 Q24In the logic circuit shown in the figure, Y is given by [figure]MCQ · +1 marks · Easy
  2. Set 1 Q25The op-amp shown in the figure is ideal. The input impedance viniin\frac{v_{in}}{i_{in}} is given by [figure]MCQ · +1 marks · Medium
  3. Set 1 Q46Which one of the following statements is true about the digital circuit shown in the figure [figure]MCQ · +2 marks · Hard
  4. Set 1 Q47Digital input signals A,B,CA, B, C with AA as the MSB and CC as the LSB are used to realize the Boolean function F=m0+m2+m3+m5+m7F = m_0 + m_2 + m_3 + m_5 + m_7, where mim_i…MCQ · +2 marks · Easy
  5. Set 1 Q51In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain β=100\beta = 100. The base-emitter voltage drop is a constant,…NAT · +2 marks · Medium

GATE EE 20178 questions

  1. Set 1 Q13The Boolean expression AB+ACˉ+BCAB + A\bar{C} + BC simplifies toMCQ · +1 marks · Easy
  2. Set 1 Q14For the circuit shown in the figure below, assume that diodes D1D_1, D2D_2 and D3D_3 are ideal. The DC components of voltages v1v_1 and v2v_2, respectively are…MCQ · +1 marks · Medium
  3. Set 1 Q35The approximate transfer characteristic for the circuit shown below with an ideal operational amplifier and diode will be [figure]MCQ · +1 marks · Medium
  4. Set 1 Q36The output expression for the Karnaugh map shown below is [figure]MCQ · +2 marks · Easy
  5. Set 1 Q37The logical gate implemented using the circuit shown below where, V1V_1 and V2V_2 are inputs (with 0 V0\text{ V} as digital 00 and 5 V5\text{ V} as digital 11)…MCQ · +2 marks · Easy
  6. Set 1 Q52The circuit shown in the figure uses matched transistors with a thermal voltage VT=25 mVV_T = 25\text{ mV}. The base currents of the transistors are negligible. The…NAT · +2 marks · Hard
  7. Set 2 Q10For a 3-input logic circuit shown below, the output ZZ can be expressed as [figure]MCQ · +2 marks · Easy
  8. Set 2 Q37For the circuit shown in the figure below, it is given that VCE=VCC2V_{CE} = \frac{V_{CC}}{2}. The transistor has β=29\beta = 29 and VBE=0.7 VV_{BE} = 0.7\text{ V} when the…MCQ · +2 marks · Medium

Other GATE EE topics

General Aptitude(181)Engineering Mathematics(173)Electric Circuits(139)Electrical Machines(129)Power Systems(108)Signals & Systems(107)Power Electronics(101)Control Systems(98)Electromagnetic Fields(56)Electrical & Electronic Measurements(36)

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