GATE CS 2022 Set 1 — Question 38

MCQ+2 / -0.67MediumPaging & Address TranslationMemory ManagementOperating SystemMultilevel & Inverted Page TablesTLB & EAT

Operating System → Memory Management → Multilevel & Inverted Page Tables

Last updated 5 September 2026

Question

Which one of the following statements is FALSE ?

Correct answer (C) The memory access time using a given inverted page table is always same for all incoming virtual addresses. Solution Let's evaluate each statement: (A) True : A Translation Lookaside Buffer (TLB) is typically implemented using Content-Addressable Memory (CAM), which allows for high-speed parallel associative searching of all entries. (B) True : A TLB hit implies that the page table entry for that virtual address is present and valid. This means the corresponding page is currently resident in physical (main) memory. A cache miss simply means the data isn't in the faster cache levels, but it must be in main memory. (C) False : Inverted page tables use a hash table to map virtual addresses to physical frames. Because of potential hash collisions, entries are often stored in chains (linked lists). Searching through these chains takes variable time depending on the length of the chain and the position of the entry, so access time is not constant. (D) True : In hashed page tables, collisions are handled by chaining. If two different virtual addresses hash to the same bucket, the system must traverse the linked list to find the correct entry. The time taken depends on the depth of the entry in the list, so the access times will likely differ. Turn this into a strength. Explore AI-powered practice and doubt support with Success Tracker.

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Correct answer (C) The memory access time using a given inverted page table is always same for all incoming virtual addresses. Solution Let's evaluate each statement: (A) True : A Translation Lookaside Buffer (TLB) is typically implemented using Content-Addressable Memory (CAM), which allows for high-speed parallel associative searching of all entries. (B) True : A TLB hit implies that the page table entry for that virtual address is present and valid. This means the corresponding page is currently resident in physical (main) memory. A cache miss simply means the data isn't in the faster cache levels, but it must be in main memory. (C) False : Inverted page tables use a hash table to map virtual addresses to physical frames. Because of potential hash collisions, entries are often stored in chains (linked lists). Searching through these chains takes variable time depending on the length of the chain and the position of the entry, so access time is not constant. (D) True : In hashed page tables, collisions are handled by chaining. If two different virtual addresses hash to the same bucket, the system must traverse the linked list to find the correct entry. The time taken depends on the depth of the entry in the list, so the access times will likely differ.

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