GATE EC 2017 Set 1 — Question 40

The circuit diagram shows an NMOS transistor with a voltage divider biasing the gate and a source resistor. We need to find the drain current $I_D$.1. Calculate Gate Voltage ($V_G$):
The gate is biased by a voltage divider formed by $R_1$ and $R_2$ from $V_{DD}$.
$V_{DD} = 8 \text{ V}$, $R_1 = 3 \text{ M}\Omega$, $R_2 = 5 \text{ M}\Omega$.
$V_G = V_{DD} \frac{R_2}{R_1 + R_2} = 8 \text{ V} \frac{5 \text{ M}\Omega}{3 \text{ M}\Omega + 5 \text{ M}\Omega} = 8 \text{ V} \frac{5}{8} = 5 \text{ V}$.2. Apply KVL to the source loop:
For an NMOS transistor, $V_{GS} = V_G - V_S$. Also, $V_S = I_D R_S$.
So, $V_{GS} = V_G - I_D R_S = 5 - I_D (1 \text{ k}\Omega)$.3. Use the saturation region current equation:
The transistor is stated to be in saturation. The drain current in saturation is given by:
$I_D = \frac{1}{2} \mu_n C_{ox} \left(\frac{W}{L}\right) (V_{GS} - V_{tn})^2$
Given $\mu_n C_{ox} \left(\frac{W}{L}\right) = 1 \text{ mA/V}^2$ and $V_{tn} = 1 \text{ V}$.
$I_D = \frac{1}{2} (1 \text{ mA/V}^2) (V_{GS} - 1)^2$
Substitute $V_{GS} = 5 - I_D (1 \text{ k}\Omega)$ into the equation. Note that $I_D$ is in mA and $R_S$ is in k$\Omega$, so $I_D R_S$ will be in V.
$I_D = \frac{1}{2} ( (5 - I_D) - 1 )^2$
$I_D = \frac{1}{2} (4 - I_D)^2$
$2I_D = (4 - I_D)^2$
$2I_D = 16 - 8I_D + I_D^2$
$I_D^2 - 10I_D + 16 = 0$4. Solve the quadratic equation for $I_D$:
Using the quadratic formula $I_D = \frac{-b \pm \sqrt{b^2 - 4ac}}{2a}$:
$I_D = \frac{10 \pm \sqrt{(-10)^2 - 4(1)(16)}}{2(1)}$
$I_D = \frac{10 \pm \sqrt{100 - 64}}{2}$
$I_D = \frac{10 \pm \sqrt{36}}{2}$
$I_D = \frac{10 \pm 6}{2}$
Two possible values for $I_D$: $I_D = \frac{10 + 6}{2} = 8 \text{ mA}$ or $I_D = \frac{10 - 6}{2} = 2 \text{ mA}$.5. Check for saturation condition:
For saturation, $V_{DS} > V_{GS} - V_{tn}$. Also, $V_{GS} > V_{tn}$.
Let's check $V_{GS}$ for both $I_D$ values:
If $I_D = 8 \text{ mA}$: $V_{GS} = 5 - 8(1) = -3 \text{ V}$. This is less than $V_{tn} = 1 \text{ V}$, so the transistor is in cutoff, not saturation. This solution is invalid.
If $I_D = 2 \text{ mA}$: $V_{GS} = 5 - 2(1) = 3 \text{ V}$. This is greater than $V_{tn} = 1 \text{ V}$, so the transistor can be in saturation.Now, let's verify the saturation condition $V_{DS} > V_{GS} - V_{tn}$ for $I_D = 2 \text{ mA}$.
$V_D = V_{DD} - I_D R_D = 8 \text{ V} - (2 \text{ mA})(1 \text{ k}\Omega) = 8 - 2 = 6 \text{ V}$.
$V_S = I_D R_S = (2 \text{ mA})(1 \text{ k}\Omega) = 2 \text{ V}$.
$V_{DS} = V_D - V_S = 6 - 2 = 4 \text{ V}$.
$V_{GS} - V_{tn} = 3 \text{ V} - 1 \text{ V} = 2 \text{ V}$.
Since $V_{DS} = 4 \text{ V} > (V_{GS} - V_{tn}) = 2 \text{ V}$, the transistor is indeed in saturation for $I_D = 2 \text{ mA}$.Thus, the drain current $I_D = 2 \text{ mA}$.The final answer is $\boxed{2.0}$.