60 solved GATE EC questions on Analog Circuits, drawn from 10 exam years and grouped by year. Every question shows the official answer and a step-by-step solution.
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These selected foundations connect device models, amplifier bias, and feedback. Separate DC bias from incremental signals before calculating gain. The original examples are symbolic DC problems with rail-limited ideal op-amps, not electrical construction guidance.
Our study notes and original examples support the PYQs below; they are not official exam questions or a replacement for the current syllabus.
Choose an ideal, constant-drop, or exponential model. An ideal conducting diode has zero voltage and nonnegative anode-to-cathode current; an off diode has zero current and nonpositive anode-to-cathode voltage. Solve the assumed state, then verify its inequalities without mixing models.
Check yourself: Does the computed diode voltage or current support the assumed state?
Verify DC bias and operating region before linearization. Small-signal gain relates increments, not total voltages. For incremental analysis, constant independent voltage sources become shorts and constant independent current sources become opens; dependent sources remain. Frequency-dependent impedances require a stated AC regime.
Check yourself: Could the predicted signal excursion leave the region used for linearization?
Mirror ratios depend on device matching, geometry, and operating region; insufficient output voltage can invalidate them. A differential pair responds to input-voltage differences around its bias point. Common-mode shifts move both inputs together and can change device operating regions.
Check yourself: Are the mirror output and pair inputs within the model's allowed voltage range?
Ideal input currents vanish. Equality v+ = v− requires stable negative feedback and unsaturated operation. Solve under that equality, then compare the output with specified rails. During saturation, use the rail voltage and recompute input nodes; equality can fail.
Check yourself: Is the proposed linear output strictly between the stated rails?
With forward gain A, feedback factor β, and error e = input − β output, linear closed-loop gain is A/(1 + Aβ). Frequency-dependent phase affects stability. For oscillation, the signed round-trip gain must reach unity at a candidate frequency; this alone guarantees neither startup nor stable amplitude.
Check yourself: Did you establish the feedback sign before applying a closed-loop formula?
Original teaching example · not a PYQ
Original mini-example: an ideal non-inverting op-amp has v+ = 0.8 V DC, 10 kΩ from v− to zero reference, and 30 kΩ from output to v−. Assume stable negative feedback, ±5 V output limits, unlimited common-mode range and output current. Find output and feedback current.
Output = 3.2 V; feedback current = 80 μA from output toward v−.
Separately, an ideal inverting op-amp has v+ = 0, input 1.5 V through 10 kΩ, and 40 kΩ feedback. Assume a static hard-clamped output at ±5 V, otherwise ideal behavior and negative feedback. Find the output and v−.
Output = −5 V and v− = 0.2 V; virtual ground is invalid.
Linear gain demands −6 V, beyond the lower rail. At output −5 V, KCL gives (v− − 1.5)/10 + (v− + 5)/40 = 0, so v− = 0.2 V. Negative differential input confirms lower-rail saturation.
Supplemental reading, not an official GATE reading list or an endorsement of these notes.
Free supplemental notes: lectures 7–11 cover incremental amplifier models; 19–21 examine op-amp abstractions, circuits, and positive feedback.
This page shows 60 recent questions from the released archive, newest first. For older questions and complete papers, browse all GATE EC papers. Questions can carry more than one subject tag; counts are not marks weightage.
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