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GATE EC 2017 Set 2 — Question 13

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MCQ+1 / -0.33MediumClamping CircuitsDiode CircuitsAnalog CircuitsZener Diode ApplicationsP-N Junction & DiodesElectronic Devices

Analog Circuits → Diode Circuits → Clamping Circuits

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Question

In the figure, D1D_1 is a real silicon pnpn junction diode with a drop of 0.7 V0.7\text{ V} under forward bias condition and D2D_2 is a Zener diode with breakdown voltage of −6.8 V-6.8\text{ V}. The input Vin(t)V_{in}(t) is a periodic square wave of period TT, whose one period is shown in the figure.
A circuit diagram showing an input voltage $V_{in}(t)$ connected to a $10\text{ }\mu\text{F}$ capacitor in series with a parallel combination of a $10\text{ }\Omega$ resistor and a branch containing two diodes $D_1$ and $D_2$ in series. $D_1$ is a standard diode pointing downwards, and $D_2$ is a Zener diode pointing upwards. The input waveform is a square wave alternating between $+14\text{ V}$ and $-14\text{ V}$ with period $T$.
Assuming 10τ≪T10\tau \ll T, where τ\tau is the time constant of the circuit, the maximum and minimum values of the output waveform are respectively,
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