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GATE EC 2018 Set 1 — Question 53

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NAT+2 / -0HardI-V & TransconductanceMOS Capacitor & MOSFETElectronic DevicesBiasing & DC Operating PointBJT & MOSFET AmplifiersAnalog Circuits

Analog Circuits → BJT & MOSFET Amplifiers → Biasing & DC Operating Point

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Question

In the circuit shown below, the (W/L)(W/L) value for M2M_2 is twice that for M1M_1. The two nMOS transistors are otherwise identical. The threshold voltage VTV_T for both transistors is 1.0V1.0V. Note that VGSV_{GS} for M2M_2 must be >1.0V> 1.0 V.
Circuit diagram and current equations for nMOS transistors
Current through the nMOS transistors can be modeled asIDS=μCox(WL)((VGS−VT)VDS−12VDS2) for VDS≤VGS−VTI_{DS} = \mu C_{ox} \left(\frac{W}{L}\right) \left((V_{GS} - V_T)V_{DS} - \frac{1}{2}V_{DS}^2\right) \text{ for } V_{DS} \le V_{GS} - V_TIDS=μCox(WL)(VGS−VT)2/2 for VDS≥VGS−VTI_{DS} = \mu C_{ox} \left(\frac{W}{L}\right) (V_{GS} - V_T)^2/2 \text{ for } V_{DS} \ge V_{GS} - V_TThe voltage (in volts, accurate to two decimal places) at VxV_x is _______.
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