GATE EC 2026 Set 1 — Question 35
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Digital Circuits → Sequential Logic → SR, D, JK & T Flip-Flops
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Question
The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of 10 cycles/second is applied to its clock (C) input.
The frequency of the output Q (in cycles/second) is
(rounded off to two decimal places)
The frequency of the output Q (in cycles/second) is
(rounded off to two decimal places)
Correct answer
4.9 to 5.1
Solution
A JK flip-flop with both J and K inputs tied to Logic High (J=1, K=1) operates in toggle mode. In toggle mode, the output Q changes state (toggles) on each active clock edge.Given:
Therefore, the frequency of the output Q is 5 cycles/second.Rounding off to two decimal places, the frequency is 5.00 cycles/second. This value falls within the specified range of 4.90 to 5.10.
- Type of flip-flop: Negative edge triggered JK flip-flop.
- Inputs: J = Logic High (1), K = Logic High (1).
- Clock input (C): Square wave with frequency cycles/second.
Therefore, the frequency of the output Q is 5 cycles/second.Rounding off to two decimal places, the frequency is 5.00 cycles/second. This value falls within the specified range of 4.90 to 5.10.
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