60 solved GATE EC questions on Digital Circuits, drawn from 9 exam years and grouped by year. Every question shows the official answer and a step-by-step solution.
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Separate combinational output (determined by present inputs) from sequential output (determined by present inputs and stored state). These selected foundations connect Boolean algebra, gate-level design, and finite-state machines. Verify each simplification by evaluating input combinations.
Our study notes and original examples support the PYQs below; they are not official exam questions or a replacement for the current syllabus.
Every Boolean function over n variables can be expressed as a sum of minterms or product of maxterms. Karnaugh maps group adjacent cells sharing a common literal; each group of 2^k cells eliminates k variables. Verify the simplified expression against the original truth table.
Check yourself: Does every minterm in the original function belong to at least one group?
A multiplexer selects one of 2^n data inputs using n select lines. A decoder maps an n-bit input to one of 2^n output lines. Propagation delay determines the time between input change and stable output; hazards are transient glitches during this window.
Check yourself: Are the select and enable signals correctly connected?
Two's complement represents signed integers: the most significant bit has a negative weight. For n bits, the range is −2^(n−1) to 2^(n−1) − 1. Overflow occurs when the result exceeds this range, not merely when a carry exists.
Check yourself: Does the sign bit of the result correctly reflect the operands' signs?
A D flip-flop samples its input at the active clock edge and holds the value until the next edge. A JK flip-flop toggles when both J and K are high. Counters chain flip-flops; synchronous counters clock all flip-flops simultaneously while asynchronous counters propagate the clock through each stage.
Check yourself: Is the data stable for the required setup window before the clock edge?
CMOS consumes negligible static power but has dynamic power proportional to switching frequency and load capacitance. Fan-out limits how many gate inputs one output can drive. Noise margin is the difference between the specified output level and the required input level. Mixing logic families requires checking voltage compatibility.
Check yourself: Is the output high level above the input high threshold of the driven gate?
Original teaching example · not a PYQ
Original mini-example: simplify F(A, B, C) = Σm(1, 3, 5, 7) using a Karnaugh map.
F = C.
A 3-bit synchronous up-counter starts at 000. What is the state after 6 clock pulses?
110 (decimal 6).
The counter increments by 1 each clock: 000→001→010→011→100→101→110. After 6 pulses, the state is 110. The counter wraps around after 111.
Supplemental reading, not an official GATE reading list or an endorsement of these notes.
Free supplemental course covering combinational logic, sequential logic, finite state machines, and digital system design.
This page shows 60 recent questions from the released archive, newest first. For older questions and complete papers, browse all GATE EC papers. Questions can carry more than one subject tag; counts are not marks weightage.
F(A, B, C) defined by three Boolean variables , and when expressed as sum of products is given by…MCQ · +1 marks · EasyContinue learning with Success Tracker
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