GATE EE 2015 Set 1 — Question 47
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Analog & Digital Electronics → Digital Logic Circuits → Latches, Flip-Flops & Counters
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Question
The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of . This state will repeat after ______ number of cycles of the clock CLK.
Correct answer
6 to 6
Solution
Step 1: Read the connectionsAll three J-K flip-flops are negative-edge triggered.
(On each falling edge of both FF1 and FF2 respond to the values present before that edge.)Step 3: CountThe circuit is a mod-6 counter: the sequence is traversed and the starting state reappears at the end of the clock pulse.Answer: 6
- FF0: , clocked by CLK, so toggles on every falling edge of CLK.
- FF1: , , clocked by .
- FF2: , , clocked by .
| CLK pulse | edge | Action on FF1 () | Action on FF2 () | |
|---|---|---|---|---|
| 1 | (rising) | none | none | 001 |
| 2 | (falling) | : toggle to 1 | : reset, stays 0 | 010 |
| 3 | none | none | 011 | |
| 4 | : toggle to 0 | : toggle to 1 | 100 | |
| 5 | none | none | 101 | |
| 6 | : reset, stays 0 | : reset to 0 | 000 |
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