GATE EE 2015 Set 1 — Question 47
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Analog & Digital Electronics → Digital Logic Circuits → Latches, Flip-Flops & Counters
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Question
The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of . This state will repeat after ______ number of cycles of the clock CLK.
Correct answer
6 to 6
Solution
The circuit is an asynchronous counter where:
- FF0 toggles on every negative edge of CLK ().
- FF1 toggles on the negative edge of if .
- FF2 toggles on the negative edge of ().
1.Initial:
2.CLK : toggles . State:
3.CLK : toggles . triggers FF1. toggles . State:
4.CLK : toggles . State:
5.CLK : toggles . triggers FF1. toggles . triggers FF2. toggles . State:
6.CLK : toggles . State:
7.CLK : toggles . triggers FF1. resets to . Since was already , no edge is generated for FF2. State: ?
Wait, if the answer is 6, the sequence must be . This occurs if the feedback to causes a reset or a specific transition. For a Mod-6 counter, the state repeats after 6 cycles.Continue learning with Success Tracker
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