GATE EE 2026 Set 1 — Question 46
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Analog & Digital Electronics → Digital Logic Circuits → Boolean Algebra & Gates
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Question
The MOSFET switches shown in the circuit are ideal.
Which of the following is the correct option for Boolean logical expression of the output (OUT), and the maximum possible power (P) consumed by the circuit?
Correct answer
(D) OUT = ABC, P = 7.5 mW
Solution
1.Analyze the circuit structure:
- The circuit consists of two branches connected to a supply.
- Branch 2: This is an NMOS inverter. The node (between the resistor and NMOS ) is pulled high when and pulled low when . Thus, .
- Branch 1: The output is pulled high through a resistor. The pull-down network consists of NMOS transistors and in parallel (based on the logic matching option D) and another NMOS transistor controlled by node in parallel with them.
- is low if any of the parallel paths in the pull-down network are conducting.
- Pull-down paths: OR .
- So, .
- Using De Morgan's laws: .
- Power is consumed when a branch conducts current from to ground.
- Branch 1 power (): Conducts when is low. .
- Branch 2 power (): Conducts when is low (i.e., ). .
- Maximum power (): Occurs when both branches conduct simultaneously. This happens when (Branch 2 conducts) and the pull-down network of Branch 1 is also active. If , then , so for Branch 1 to conduct, we need or .
- For , .
The expression is and the maximum power is , which corresponds to option (D).
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