GATE EE 2026 Set 1 — Question 46
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Analog & Digital Electronics → Digital Logic Circuits → Boolean Algebra & Gates
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Question
The MOSFET switches shown in the circuit are ideal.
Which of the following is the correct option for Boolean logical expression of the output (OUT), and the maximum possible power (P) consumed by the circuit?
Correct answer
(D) OUT = AB C, P = 7.5 mW
Solution
Step 1 - the right-hand branch fixes node The resistor pulls node up to V and the NMOS gated by pulls it down to 0. This is a resistive-load NMOS inverter, soStep 2 - the output branch is pulled up through the resistor. Its pull-down network is the series pair of NMOS devices driven by and , in parallel with a third NMOS whose gate is node . is pulled low when either path conducts, i.e. when or when :Step 3 - maximum powerA branch draws current from the supply only while its pull-down path conducts:Both branches conduct together for : turns on the device of the second branch, and turns on the series pair of the first branch. HenceStep 4 - pick the optionOptions (A) and (D) carry the same logic function, since , but (A) quotes mW, which ignores the current drawn by the second branch. Options (B) and (C) do not match the derived function.Answer: (D) , mW
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