GATE EE 2016 Set 1 — Question 46
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Analog & Digital Electronics → Digital Logic Circuits → Latches, Flip-Flops & Counters
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Question
The current state of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is
Correct answer
(C) 11
Solution
From the given circuit diagram, we can determine the input logic for each JK flip-flop:
Next State Calculation:
On the next active clock edge (negative edge triggered as indicated by the bubble on the CLK input):
1.Flip-flop A ():
- The input () is connected to the 5V supply rail, so .
- The input () is also connected to the 5V supply rail, so .
- The input () is connected to the 5V supply rail, so .
- The input () is connected to the output of the first flip-flop, so .
Next State Calculation:
On the next active clock edge (negative edge triggered as indicated by the bubble on the CLK input):
- For FF A: . Since both and are high, the flip-flop toggles its state. Thus, .
- For FF B: The inputs are and . Since and , the flip-flop is in the 'Set' condition. Thus, .
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