GATE EE 2021 Set 1 — Question 32
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.NAT+1 / -0MediumLatches, Flip-Flops & CountersDigital Logic CircuitsAnalog & Digital Electronics
Analog & Digital Electronics → Digital Logic Circuits → Latches, Flip-Flops & Counters
Last updated
Question
A 16-bit synchronous binary up-counter is clocked with a frequency . The two most significant bits are OR-ed together to form an output . Measurements show that is periodic, and the duration for which remains high in each period is ms. The clock frequency is ______ MHz. (Round off to 2 decimal places.)
Correct answer
2 to 2.1
Solution
A 16-bit counter has states. Let the bits be , where is the MSB.
In one full cycle of clock pulses:
Number of states where is high = states.
Given the duration ms, we have:
s
Hz = MHz.
Rounding to 2 decimal places, we get MHz.
In one full cycle of clock pulses:
- is high for states to (32768 states).
- is high for states to and to .
Number of states where is high = states.
Given the duration ms, we have:
s
Hz = MHz.
Rounding to 2 decimal places, we get MHz.
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE EE question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Digital Logic Circuits
2026 Set 1 Q33In the linear regulator circuit shown, the base to emitter voltage of the BJT is…2026 Set 1 Q37In the circuit shown, the open loop gain of the operational amplifier is . What is the…2026 Set 1 Q45The digital circuit shown has 3 inputs (, , and ). The simplified logical expression for…2026 Set 1 Q46The MOSFET switches shown in the circuit are ideal. [figure] Which of the following is the correct…2026 Set 1 Q61Consider the circuit shown. Assume that the diode () is ideal. Given …