GATE EC 2014 Set 1 — Question 50
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.MCQ+2 / -0.67EasyBoolean Algebra & IdentitiesCombinational LogicDigital Circuits
Digital Circuits → Combinational Logic → Boolean Algebra & Identities
Last updated
Question
The output F in the digital logic circuit shown in the figure is

Correct answer
(A) F = XYZ + XYZ
Solution
Let's analyze the given digital logic circuit.
Since , the first and fourth terms are zero.
Using the identities and :
This result is not present in any of the options. This indicates a likely typo in the question's diagram. A common error in such problems is misrepresenting an XOR gate as an XNOR gate or vice versa.Let's assume the second gate was intended to be an XOR gate instead of an XNOR gate. In this case, its output would be .The final output would then be:
Again, since , the first and fourth terms are zero.
This expression can be rearranged as , which matches option (A).Given that this is a standard exam question and one of the options is expected to be correct, it is highly probable that the diagram contains a typo and the XNOR gate should have been an XOR gate.Therefore, based on this correction, the correct option is A.
1.The first gate is an XOR gate with inputs X and Y. Its output is .
2.The second gate is an XNOR gate with inputs Y and Z. Its output is .
3.The third gate is an AND gate with inputs A and B. Its output is the final output F.
.Let's expand this expression:Since , the first and fourth terms are zero.
Using the identities and :
This result is not present in any of the options. This indicates a likely typo in the question's diagram. A common error in such problems is misrepresenting an XOR gate as an XNOR gate or vice versa.Let's assume the second gate was intended to be an XOR gate instead of an XNOR gate. In this case, its output would be .The final output would then be:
Again, since , the first and fourth terms are zero.
This expression can be rearranged as , which matches option (A).Given that this is a standard exam question and one of the options is expected to be correct, it is highly probable that the diagram contains a typo and the XNOR gate should have been an XOR gate.Therefore, based on this correction, the correct option is A.
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE EC question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Combinational Logic
2026 Set 1 Q20In the circuit shown in the Figure, A and B are logic inputs and Y is the logic output. Which of…2026 Set 1 Q27A binary ripple counter is designed to count to . Which of the following…2026 Set 1 Q35The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a…2026 Set 1 Q42The address of the first location of a 256 kilo byte (KB) memory is . Choose the correct…2026 Set 1 Q45What is the complement of ?