GATE EC 2014 Set 2 — Question 50
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Digital Circuits → Combinational Logic
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Question
In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4.
Correct answer
(C) W3
Solution
Both D flip-flops have a bubble on the clock input, so they are negative-edge triggered: at each falling edge of Clk, takes the value of and the value of , and changes only at falling edges.Sample and at the four falling clock edges in the timing diagram:
So stays 0 and goes high only at the 4th falling edge.
| Falling edge | |||
|---|---|---|---|
| 1st | 0 | 1 | 0 |
| 2nd | 1 | 0 ( fell just before the edge) | 0 |
| 3rd | 1 | 0 | 0 |
| 4th | 1 | 1 | 1 |
- W1 is high during the 2nd clock period: wrong.
- W2 and W4 toggle several times and change at rising edges: wrong.
- W3 is low until the 4th falling edge and then high: correct.
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