GATE EC 2014 Set 3 — Question 25
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Digital Circuits → Sequential Logic → Race-Around & Master-Slave
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Question
The circuit shown in the figure is a
Correct answer
(D) Master-Slave D Flip Flop
Solution
The circuit consists of two D-latches connected in series. The first latch (master) is enabled when the clock signal is high. The second latch (slave) is enabled when is low (due to the inverter). This configuration, where one latch captures data while the other is disabled and then passes it on the next clock phase, constitutes a Master-Slave D Flip Flop, which is edge-triggered.
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