GATE EC 2014 Set 3 — Question 50
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Digital Circuits → Semiconductor Memories → SRAM & DRAM
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Question
If is the Word Line and the Bit Line, an SRAM cell is shown in
Correct answer
(B) [figure]
Solution
A 6T SRAM cell is two cross-coupled CMOS inverters (each inverter: PMOS pull-up, NMOS pull-down; the output of each drives the input of the other) plus two NMOS access transistors whose gates are on and which connect the two storage nodes to and .
- (A) Each access transistor connects only to the gate of one inverter; the inverter outputs are not fed back to the other inverter, so there is no latch and nothing is stored. Wrong.
- (B) The two inverters are cross-coupled (output of each tied to the gates of the other) and the storage nodes are reached through NMOS access transistors driven by . This is the standard 6T SRAM cell. Correct.
- (C) The access devices (and the pull-down devices) are drawn as PMOS, so these are not CMOS inverters with NMOS pass gates; with high the cell would be isolated, and the pull-downs cannot pull the nodes to ground properly. Wrong.
- (D) The pull-up devices are drawn as NMOS, so the "inverters" are not CMOS inverters and cannot hold a full logic high. Wrong.
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