GATE EC 2014 Set 4 — Question 51
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Digital Circuits → Combinational Logic → Adders & Subtractors
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Question
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________.
Correct answer
194.9 to 195.1
Solution
In an -bit ripple carry adder, the worst-case delay occurs when the carry must propagate through all stages to produce the final sum bit. The delay for the -th stage sum bit is given by:
For a 16-bit adder (), the worst-case delay is the time taken for the last sum bit to be stable:
Given , ns, and ns:
ns.
For a 16-bit adder (), the worst-case delay is the time taken for the last sum bit to be stable:
Given , ns, and ns:
ns.
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