GATE EC 2015 Set 1 — Question 47
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Digital Circuits → Combinational Logic → Combinational Hazards
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Question
All the logic gates shown in the figure have a propagation delay of 20 ns. Let and until time . At , all the inputs flip (i.e., and ) and remain in that state. For , output for a duration (in ns) of ________.
Correct answer
40 to 40
Solution
The circuit implements the logic function .
Delays: NOT = 20 ns, AND = 20 ns, XOR = 20 ns.Initial state ():
(after 20 ns delay)
(after 40 ns delay)
(after 60 ns delay)At : .
Duration = ns.
Delays: NOT = 20 ns, AND = 20 ns, XOR = 20 ns.Initial state ():
(after 20 ns delay)
(after 40 ns delay)
(after 60 ns delay)At : .
1.Path
C → Z: changes at . will change at ns due to the XOR gate delay.2.Path :
- changes at .
- changes at , so changes at ns.
- The AND gate output changes at ns.
- This change reaches the XOR gate, and changes (since ) at ns.
Duration = ns.
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