GATE EC 2015 Set 2 — Question 26
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Digital Circuits → Sequential Logic → Ripple & Synchronous Counters
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Question
A mod- counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of is ________.
Correct answer
7 to 7
Solution
From the figure, the 2-input NAND gate takes and (dots on the and lines), and its output drives the active-low synchronous .With as the LSB, goes low when . Counting up from 0, this first happens in state (states 0 to 5 all have ).Because the clear is synchronous, the counter stays in state 6 until the next clock edge, which loads 0000 instead of 0111. The counter therefore cycles throughwhich is 7 distinct states.(Had the clear been asynchronous, state 6 would only appear as a glitch, giving mod 6.)Answer:
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