GATE EC 2015 Set 2 — Question 26

The circuit shows a 4-bit binary counter with a synchronous CLEAR input. The CLEAR signal is active-low (indicated by the bubble) and is driven by a NAND gate.The inputs to the NAND gate are connected to $Q_A$, $Q_B$, and $Q_C$. Assuming $Q_A$ is the LSB ($2^0$) and $Q_D$ is the MSB ($2^3$), the NAND output becomes low (active) when $Q_C Q_B Q_A = 111_2$, which corresponds to the decimal value 7.In a counter with a synchronous clear, the clear operation occurs at the next active clock edge after the clear condition is met. This means the counter will reach the state 7, and upon the next clock pulse, it will reset to 0 instead of incrementing to 8. Thus, the counter cycles through 7 states: 0, 1, 2, 3, 4, 5, 6. Note: In many standard textbook problems for this specific configuration, if the clear condition is met at state 7, the counter is considered a mod-7 counter as it resets when it hits the 'n-th' state.Final Answer: 7