GATE EC 2016 Set 1 — Question 28

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MCQ+1 / -0.33EasyCMOS VTC & Noise MarginCombinational LogicDigital CircuitsStatic CMOS Logic Gates

Digital Circuits → Combinational Logic → CMOS VTC & Noise Margin

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Question

What is the voltage VoutV_{out} in the following circuit?
A CMOS inverter circuit with a $10\text{ k}\Omega$ resistor connected in a feedback loop from the output node to the common gate input node of the PMOS and NMOS transistors. The source of the PMOS is connected to $V_{DD}$ and the source of the NMOS is connected to ground.
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