GATE EC 2016 Set 1 — Question 53
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Digital Circuits → Combinational Logic → MUX, DEMUX, Decoders & Encoders
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Question
The functionality implemented by the circuit below is
📷 Figure: Tristate buffer symbol
is a tristate bufferCorrect answer
(B) 4-to-1 multiplexer
Solution
The circuit consists of a 2:4 decoder and four tristate buffers. The decoder has two select lines and , which generate four output signals . Each of these signals acts as an enable for one of the four tristate buffers. The inputs to the buffers are P, Q, R, and S. Depending on the values of and , exactly one of the tristate buffers will be enabled, passing its input (P, Q, R, or S) to the common output Y. This is the standard implementation of a 4-to-1 multiplexer using a decoder and tristate buffers.
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