GATE EC 2016 Set 2 — Question 53
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Digital Circuits → Data Converters → ADC (Flash, SAR, Dual-Slope)
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Question
In an bit flash ADC, the analog voltage is fed simultaneously to comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source (whose output is being converted to digital format) has a source resistance of as shown in the circuit diagram below and the input capacitance of each comparator is . The input must settle to an accuracy of LSB even for a full scale input change for proper conversion. Assume that the time taken by the thermometer to binary encoder is negligible.
If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate ?
Correct answer
(A) 1 megasamples per second
Solution
1.Identify parameters: bits, , .
2.Total input capacitance: .
3.Time constant: .
4.Settling requirement: For LSB accuracy, the error must be .
.5.Calculate settling time: .
6.Maximum sampling rate: .
The closest alternative is 1 megasamples per second.Continue learning with Success Tracker
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