GATE EC 2017 Set 1 — Question 15
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.MCQ+1 / -0.33MediumSR & D LatchesSequential LogicDigital Circuits
Digital Circuits → Sequential Logic → SR & D Latches
Last updated
Question
In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: . If the input condition is changed simultaneously to , the outputs and are
Correct answer
(B) either X = '1', Y = '0' or X = '0', Y = '1'
Solution
The circuit is a NAND-based SR latch.
1.Initial state: . For a NAND gate, if any input is 0, the output is 1. Thus, and .
2.Transition: and both change to 1.
3.Now, the top NAND gate has inputs and , so its output tends to . The bottom NAND gate has inputs and , so its output tends to .
4.Since the propagation delays are unequal, one gate will switch to 0 faster than the other.
5.If the top gate is faster, becomes 0 first. This 0 is fed back to the bottom gate, making its inputs and , so stays at .
6.If the bottom gate is faster, becomes 0 first. This 0 is fed back to the top gate, making its inputs and , so stays at .
7.Therefore, the final state will be either or .
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE EC question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Sequential Logic
2026 Set 1 Q20In the circuit shown in the Figure, A and B are logic inputs and Y is the logic output. Which of…2026 Set 1 Q27A binary ripple counter is designed to count to . Which of the following…2026 Set 1 Q35The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a…2026 Set 1 Q42The address of the first location of a 256 kilo byte (KB) memory is . Choose the correct…2026 Set 1 Q45What is the complement of ?