GATE EC 2017 Set 1 — Question 17
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Digital Circuits → Sequential Logic → SR & D Latches
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Question
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output of the latch in percentage is _________.
Correct answer
29.9 to 30.1
Solution
1.Analyze the signals: Let the period of the clock signals be .
- CLK1 has a 50% duty cycle, so it is high for and low for .
- CLK2 is a one-fifth period delayed version of CLK1, so it is high for and low for .
3.Determine Output :
- In the interval , CLK2 is high (transparent mode):
- From to , , so .
- From to , , so .
- At , CLK2 goes low (hold mode). The latch holds the value .
- remains until the next transparency interval starts at .
- The high time of in one period is .
- Duty cycle = .
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