GATE EC 2017 Set 1 — Question 46
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Digital Circuits → Sequential Logic → FSM (Mealy & Moore)
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Question
A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are and . Assume that is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state and clocked, after a few clock cycles, it starts cycling through
Correct answer
(D) (D) only two of the four possible states if X_(IN) = 0
Solution
From the circuit diagram, the next-state equations for the flip-flops are:
(NAND gate)Let's analyze the state transitions starting from for both cases of :Case 1:
(always)
(NAND gate)Let's analyze the state transitions starting from for both cases of :Case 1:
(always)
- Initial state:
- Next state: ,
- Next state: ,
- Next state: ,
- Initial state:
- Next state: ,
- Next state: ,
- Next state: ,
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