GATE EC 2018 Set 1 — Question 42
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Digital Circuits → Semiconductor Memories → ROM, PROM, EPROM & EEPROM
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Question
A ROM array is built with the help of diodes as shown in the circuit below. Here and are signals that select the word lines and and are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation.
During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to (where or and or ) stored in the ROM?
Correct answer
(A) bmatrix 1 & 0 \ 0 & 1 bmatrix
Solution
Each bit line is pulled to ground by an nMOS (gate at ), so it reads 0 unless a diode from the selected (high) word line pulls it up.
- high: there is a diode from to , so ; no diode to , so . Hence , .
- high: no diode to , so ; a diode from to , so . Hence , .
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