GATE EC 2020 Set 1 — Question 46

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MCQ+2 / -0.67HardSample & HoldData ConvertersDigital CircuitsMOSFET Structure & OperationMOS Capacitor & MOSFETElectronic Devices

Digital Circuits → Data Converters → MOSFET Structure & Operation

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Question

An enhancement MOSFET of threshold voltage 3 V3\text{ V} is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to 10 V-10\text{ V}. If the input voltage ViV_i lies between ±10 V\pm 10\text{ V}, the minimum and the maximum values of VGV_G required for proper sampling and holding respectively, are
MOSFET sample and hold circuit diagram
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