GATE EC 2021 Set 1 — Question 56
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Digital Circuits → Sequential Logic → Setup, Hold & Propagation Delay
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Question
The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns. The propagation delay of all the flip-flops is assumed to be zero. The clock (Clk) frequency provided to the circuit is 500 MHz.
Starting from the initial value of the flip-flop outputs with , the minimum number of triggering clock edges after which the flip-flop outputs becomes (in integer) is _________.
Solution
Circuit (from the figure). (the XOR's inputs are fed back from and ), , . So each edge loadsClock period ns. The XOR output changes 3 ns after its inputs change. The flip-flops have zero delay.At the outputs are and . The XOR inputs are , so falls to at ns.Official count (first edge at , so edges at 0, 2, 4, 6, 8 ns).
The outputs become after 5 edges, which is the official answer.Why 4 is also accepted. The question does not fix where the first edge falls relative to the moment the outputs became . If the first edge arrives more than 1 ns after that moment (for example, edges at 2, 4, 6, 8 ns), the XOR has already switched to by the second edge:
This takes only 4 edges, and the question asks for the minimum. A transport-delay simulation over every clock phase gives exactly these two outcomes: 5 when the first edge comes within 1 ns, and 4 otherwise.Answer: 5 (official); 4 is also accepted
| Edge | Time | at the edge (from XOR inputs 3 ns earlier) | New |
|---|---|---|---|
| 1 | 0 ns | 1 (initial value) | 111 |
| 2 | 2 ns | 1 (XOR has not switched yet) | 111 |
| 3 | 4 ns | (state 111 at 1 ns) | 011 |
| 4 | 6 ns | (state 111 at 3 ns) | 001 |
| 5 | 8 ns | (state 011 at 5 ns) | 100 |
| Edge | Time | New | |
|---|---|---|---|
| 1 | 2 ns | 1 | 111 |
| 2 | 4 ns | 0 (state 111 at 1 ns) | 011 |
| 3 | 6 ns | 0 (state 111 at 3 ns) | 001 |
| 4 | 8 ns | 1 (state 011 at 5 ns) | 100 |
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