GATE EC 2021 Set 1 — Question 56
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Digital Circuits → Sequential Logic → Setup, Hold & Propagation Delay
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Question
The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns. The propagation delay of all the flip-flops is assumed to be zero. The clock (Clk) frequency provided to the circuit is 500 MHz.
Starting from the initial value of the flip-flop outputs with , the minimum number of triggering clock edges after which the flip-flop outputs becomes (in integer) is _________.
Correct answer
5 to 5
Solution
Given clock frequency , the clock period is . The XOR gate delay is .
Let's trace the state at each clock edge:
Let's trace the state at each clock edge:
1.Edge 1 (): . It is given that initially. The XOR inputs are and . The XOR output will change to after 3 ns.
2.Edge 2 (): Since , is still 1. Thus, . State remains .
3.At : becomes 0.
4.Edge 3 (): is 0. . State is . XOR inputs are , so stays 0.
5.Edge 4 (): is 0. . State is . XOR inputs are , so will change to 1 after 3 ns (at ).
6.Edge 5 (): Since , is still 0. . State is .
7.At : becomes 1.
8.Edge 6 (): is 1. . State is .
The target state is reached at Edge 6. The number of edges after the initial Edge 1 is .Continue learning with Success Tracker
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