GATE EC 2023 Set 1 — Question 24
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Digital Circuits → Sequential Logic → Shift Registers
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Question
The synchronous sequential circuit shown below works at a clock frequency of GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are
Correct answer
(A) 1000, 3
Solution
The circuit consists of three D flip-flops connected in series, forming a pipeline.
1.Throughput: In a synchronous pipelined circuit, one new data bit can be processed every clock cycle. Given the clock frequency GHz, the throughput is bit/cycle cycles/s bits/s Mbits/s.
2.Latency: Latency is the total time taken for a single bit to travel from the input to the output. Since there are 3 flip-flops, it takes 3 clock cycles for a bit to reach the output. Latency ns.
Thus, the throughput is Mbits/s and the latency is ns.Continue learning with Success Tracker
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