GATE EC 2024 Set 1 — Question 51
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Digital Circuits → Combinational Logic → MUX, DEMUX, Decoders & Encoders
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Question
In the circuit shown below, the transistors and are biased in saturation. Their small signal transconductances are and respectively. Neglect body effect, channel length modulation and intrinsic device capacitances.
📷 Figure: Circuit: I_ref from V_DD into diode-connected NMOS M1 (source grounded); M1 gate/drain connects through R_B to the gate of common-source NMOS M2 (drain to V_DD via R_D, output v_out at drain); v_in drives the M2 gate through R_S in series with capacitor C1
Assuming that capacitor is a short circuit for AC analysis, the exact magnitude of small signal voltage gain is ______.Correct answer
(B) gₘ₂R_D(R_B + 1gₘ₁)R_B + 1gₘ₁ + Rₛ
Solution
AC model. is an ideal current source (open for AC). is diode-connected (gate tied to drain), so with no channel-length modulation it looks like a resistance to ground. is a short. The gate of draws no current.So from the gate node to AC ground there is in series, and reaches that node through . Voltage divider:Common-source stage (, source grounded, load ):
- (A) ignores the input divider.
- (C) inverts the divider (gain larger than , impossible for a passive divider).
- (D) drops from the shunt path.
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