GATE EC 2025 Set 1 — Question 62

Given parameters:
Clock-to-Q delay ($t_{CQ}$) of flip-flops = 2 ns
AND gate propagation delay ($t_{AND}$) = 1 ns
Setup time ($t_{setup}$) of flip-flops = 2 ns
Hold time ($t_{hold}$) of flip-flops = 0 nsFor no setup violation, the data must arrive at the D input of the second flip-flop before the next rising edge of the clock, considering the setup time.The critical path for data to reach the D input of the second flip-flop (FF2) starts from the Q output of the first flip-flop (FF1) and goes through the AND gate.
Total delay for data to reach D of FF2 ($t_{data}$) = $t_{CQ} + t_{AND}$
$t_{data} = 2 \text{ ns} + 1 \text{ ns} = 3 \text{ ns}$.The minimum clock period ($T_{CLK,min}$) required to avoid setup violations is given by:
$T_{CLK,min} \ge t_{data} + t_{setup}$
$T_{CLK,min} \ge 3 \text{ ns} + 2 \text{ ns} = 5 \text{ ns}$.The maximum clock frequency ($f_{CLK,max}$) is the reciprocal of the minimum clock period:
$f_{CLK,max} = \frac{1}{T_{CLK,min}} = \frac{1}{5 \text{ ns}} = \frac{1}{5 \times 10^{-9} \text{ s}}$
$f_{CLK,max} = 0.2 \times 10^9 \text{ Hz} = 200 \times 10^6 \text{ Hz} = 200 \text{ MHz}$.We also need to check for hold time violations. The condition for no hold time violation is:
$t_{CQ,min} + t_{AND,min} \ge t_{hold}$
Assuming minimum delays are the same as given (2 ns + 1 ns = 3 ns):
$3 \text{ ns} \ge 0 \text{ ns}$.
Since this condition is satisfied, there are no hold time violations.Therefore, the maximum clock frequency is 200 MHz.The final answer is $\mathbf{200}$.