GATE EE 2014 Set 1 — Question 60
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.MCQ+2 / -0.67MediumK-Map MinimizationDigital Logic CircuitsAnalog & Digital Electronics
Analog & Digital Electronics → Digital Logic Circuits → K-Map Minimization
Last updated
Question
Which of the following logic circuits is a realization of the function whose Karnaugh map is shown in figure
Correct answer
(C) [figure]
Solution
Step 1 - read the Karnaugh map. The columns are and the rows are . The cells containing 1 are
, , and .Step 2 - simplify.
, , and .Step 2 - simplify.
- The pair in row , columns and : here and while changes, giving .
- The pair in row , columns and : here and while changes, giving .
- (A) The NAND gate with both inputs tied to gives ; the other gate gives ; these feed an AND gate, so . Not (for example gives but ).
- (B) and are combined in an OR gate, so . For this gives 1, whereas . Not .
- (C) and are each inverted by a NAND gate and the two results are ANDed, giving ; a second AND gate forms ; the output OR gate gives
- (D) The NAND gate inverts , and is ANDed with , giving ; the second AND gate gives ; the OR gate gives . Not (for , but ).
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE EE question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Digital Logic Circuits
2026 Set 1 Q33In the linear regulator circuit shown, the base to emitter voltage of the BJT is…2026 Set 1 Q37In the circuit shown, the open loop gain of the operational amplifier is . What is the…2026 Set 1 Q45The digital circuit shown has 3 inputs (, , and ). [figure] The simplified logical…2026 Set 1 Q46The MOSFET switches shown in the circuit are ideal. [figure] Which of the following is the correct…2026 Set 1 Q61Consider the circuit shown. Assume that the diode () is ideal. Given …