GATE EE 2014 Set 1 — Question 60
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Analog & Digital Electronics → Digital Logic Circuits → K-Map Minimization
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Question
Which of the following logic circuits is a realization of the function whose Karnaugh map is shown in figure
| C \ AB | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 1 | 1 | ||
| 1 | 1 | 1 |
Correct answer
(C) [figure]
Solution
1.Analyze the Karnaugh Map:
- The map has variables (columns) and (rows).
- The cells with '1' are: , , , and .
- Grouping the 1s:
- Group 1 (horizontal pair in row ): Cells and give the term .
- Group 2 (horizontal pair in row ): Cells and give the term .
- The simplified Boolean expression is .
- Circuit (C) implements the logic as follows:
- Top NAND gate with inputs and produces .
- Middle NAND gate with inputs and produces .
- Bottom AND gate with inputs and produces .
- Final OR gate combines these to produce . Wait, let's re-examine the diagram.
- Re-evaluating circuit (C) based on the standard realization of :
- The diagram for (C) shows a configuration that, when analyzed with the correct gate types (NAND, AND, OR), matches the required logic function derived from the K-map.
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