GATE EE 2014 Set 1 — Question 62
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.MCQ+2 / -0.67MediumMUX, DEMUX, DecodersDigital Logic CircuitsAnalog & Digital Electronics
Analog & Digital Electronics → Digital Logic Circuits → MUX, DEMUX, Decoders
Last updated
Question
An output device is interfaced with 8-bit microprocessor 8085A. The interfacing circuit is shown in figure.
The interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enable lines . The address of the device is
Correct answer
(B) 5000_H
Solution
Step 1 - which decoder output is used. The Output Port is enabled from decoder output line , so the select inputs must beThe select inputs are driven by the address bus as , , , henceStep 2 - the enable conditions.
- is active high and is driven by an AND gate whose inputs are and with the input inverted, so . For we need
- is tied to , so the decoder is enabled only when . The port is therefore memory mapped and the complete 16-bit address bus is decoded.
- is tied to , so the port is selected during a write (output) machine cycle.
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE EE question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Digital Logic Circuits
2026 Set 1 Q33In the linear regulator circuit shown, the base to emitter voltage of the BJT is…2026 Set 1 Q37In the circuit shown, the open loop gain of the operational amplifier is . What is the…2026 Set 1 Q45The digital circuit shown has 3 inputs (, , and ). [figure] The simplified logical…2026 Set 1 Q46The MOSFET switches shown in the circuit are ideal. [figure] Which of the following is the correct…2026 Set 1 Q61Consider the circuit shown. Assume that the diode () is ideal. Given …