GATE EE 2014 Set 3 — Question 31
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Analog & Digital Electronics → Digital Logic Circuits → Boolean Algebra & Gates
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Question
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where is the don’t care condition, and is the output representing the state.
Correct answer
(D) NAND
Solution
The state diagram shows the transitions for a logic gate with delay, where is the current output state. Let the inputs be and .
- From state (output is ):
- If input is , the system stays in (loop label ).
- If input is or (i.e., ), the system transitions to (arrow label ).
- From state (output is ):
- If input is or (i.e., ), the system stays in (loop label ).
- If input is , the system transitions to (arrow label ).
- Input Output becomes .
- Input Output becomes .
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