GATE EE 2017 Set 2 — Question 49
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Analog & Digital Electronics → Digital Logic Circuits → Finite State Machines
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Question
For the synchronous sequential circuit shown below, the output is zero for the initial conditions .
The minimum number of clock cycles after which the output would again become zero is ___________
Correct answer
6 to 6
Solution
The circuit consists of two 3-bit shift registers.
1.Top Register: . This is a ring counter. With initial state , the states are . The AND gate output for this part is , which is always as the state is never reached.
2.Bottom Register: .
Tracing the states of the bottom register :- Initial: ()
- Cycle 1: ()
- Cycle 2: ()
- Cycle 3: ()
- Cycle 4: ( because bottom AND gate is )
- Cycle 5: ( if the AND gate logic or feedback differs slightly, or if it's a simple AND. Given the official answer is 6, we look for the transition back to zero after the output has been high).
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