GATE EE 2017 Set 2 — Question 49
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Analog & Digital Electronics → Digital Logic Circuits → Finite State Machines
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Question
For the synchronous sequential circuit shown below, the output is zero for the initial conditions .
The minimum number of clock cycles after which the output would again become zero is ___________
Correct answer
6 to 6
Solution
The output gate network compares the two registers bit by bit:So only when the upper register and the lower register hold the same state, and otherwise.Upper register (ring counter). The feedback comes from the uncomplemented output of the last flip-flop, so , , . Starting from :Its sequence repeats with period .Lower register (twisted-ring / Johnson counter). Here the feedback is taken from the complemented output of the last flip-flop, so , , . Starting from :Its sequence repeats with period .Clock-by-clock comparison
The two registers are identical again only when both sequences simultaneously return to , i.e. after clock cycles, and the table confirms that no earlier clock gives a match.Answer: 6
| Clock | |||
|---|---|---|---|
| 0 | 100 | 100 | 0 |
| 1 | 010 | 110 | 1 |
| 2 | 001 | 111 | 1 |
| 3 | 100 | 011 | 1 |
| 4 | 010 | 001 | 1 |
| 5 | 001 | 000 | 1 |
| 6 | 100 | 100 | 0 |
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