GATE EC 2015 Set 2 — Question 47

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MCQ+2 / -0.67MediumRipple & Synchronous CountersSequential LogicDigital Circuits

Digital Circuits → Sequential Logic → Ripple & Synchronous Counters

Last updated 5 September 2026

Question

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

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Correct answer (C) mod-5 counter Solution The question is known to be flawed in the official GATE 2015 paper. The provided diagram and the official answer are inconsistent. We will analyze both the diagram as given and the likely intended circuit that leads to the correct answer. Analysis of the Diagram as Given: 1. The circuit has a binary counter with a synchronous clear (CLR) input. 2. The decoding logic is an OR gate with inputs Q₂ and Q₁. So, the clear condition is CLR = Q₂ + Q₁. 3. The clear is synchronous, meaning the counter will reset to 000 on the next clock edge if the CLR input is high. 4. Let's trace the states (Q₂Q₁Q₀): State 0 (000): CLR = 0 + 0 = 0. Counter proceeds to the next state. State 1 (001): CLR = 0 + 0 = 0. Counter proceeds to the next state. State 2 (010): CLR = 0 + 1 = 1. The CLR condition is met. On the next clock edge, the counter will reset to 000. 5. The sequence of states is 000, 001. The counter has 2 stable states. Therefore, based on the diagram, it is a mod-2 counter. Analysis based on the Official Answer: 1. The official answer key indicates (C) mod-5 counter. 2. For a counter to be mod-5, it must count 5 states (0, 1, 2, 3, 4) and reset when it reaches state 5 (101). 3. The clear condition must become true at state 5 (Q₂Q₁Q₀ = 101). 4. A simple logic to detect state 5 is Q₂ AND Q₀. If CLR = Q₂ \cdot Q₀, let's trace the states: States 0 to 4 (000 to 100): The condition Q₂ \cdot Q₀ is false (CLR=0). State 5 (101): The condition Q₂ \cdot Q₀ becomes true (CLR=1). On the next clock edge, the counter resets to 000. 5. This sequence (0, 1, 2, 3, 4) has 5 states, making it a mod-5 counter. 6. This implies that the question intended the decoding logic to be an AND gate with inputs Q₂ and Q₀, despite drawing an OR gate with inputs Q₂ and Q₁. Given the discrepancy, we follow the official answer, which implies the intended circuit was for a mod-5 counter.

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GATE EC 2015 Set 2 — Question 47

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