GATE EC 2015 Set 2 — Question 47
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Digital Circuits → Sequential Logic → Ripple & Synchronous Counters
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Question
The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a
Correct answer
(C) mod-5 counter
Solution
From the figure, and of the 4-bit counter drive an XNOR gate whose output feeds the active-low synchronous clear :The counter is cleared (on the next clock edge) when , i.e. when .Starting from 0000:
- 0000, 0001, 0010, 0011: , so and counting continues.
- 0100: , so ; because the clear is synchronous, the state 0100 lasts one full clock period and the next edge loads 0000.
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