GATE EC 2015 Set 2 — Question 48

Solution

The problem asks for the correct connections to terminals P, Q, R, and S to implement a 1-to-8 demultiplexer using two 2-to-4 decoders.Standard Implementation of 1-to-8 Demux using 2-to-4 Decoders:

• When $S_2=0$, the first decoder (producing outputs $Y_0$ to $Y_3$) should be enabled.
• When $S_2=1$, the second decoder (producing outputs $Y_4$ to $Y_7$) should be enabled.

3. The lower-order address bits, $S_1$ and $S_0$, are connected to the address inputs ($A_1$ and $A_0$) of both decoders.

• Enable for Decoder 1 (Y0-Y3): $E_1 = D_{in} \cdot S_2'$
• Enable for Decoder 2 (Y4-Y7): $E_2 = D_{in} \cdot S_2$

Analyzing the Given Circuit:Combining these deductions, the connections for (P, Q, R, S) should be ($D_{in}$, $S_2$, $S_0$, $S_1$). This matches option (D).Note on the Flawed Diagram:
The logic gates shown in the diagram ($1E = P+Q$ and $2E = Q'$) do not correctly implement the required demultiplexer enable logic ($E_1 = D_{in} \cdot S_2'$ and $E_2 = D_{in} \cdot S_2$). Substituting the derived connections (P=$D_{in}$, Q=$S_2$) into the diagram's logic gives $1E = D_{in} + S_2$ and $2E = S_2'$, which is incorrect. However, the question asks for the intended connections, and based on standard design principles, the assignment in option (D) is the only logical choice for the roles of the terminals.Therefore, the correct answer is based on the intended function despite the error in the provided schematic's logic gates.