GATE EC 2015 Set 2 — Question 48
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Digital Circuits → Combinational Logic → MUX, DEMUX, Decoders & Encoders
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Question
A 1-to-8 demultiplexer with data input , address inputs , , (with as the LSB) and to as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with active-low enable input and address inputs and ) as shown in the figure. , , and are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be
Correct answer
(D) Dᵢₙ, S₂, S₀, S₁
Solution
Reading the figure. Both decoders have active-low enables. Terminal R drives and , terminal S drives and . The first decoder is enabled by , i.e. only when and . The second decoder is enabled by , i.e. only when and .Assigning the inputs.
- R and S feed the address pins of both decoders, so they are the low-order select bits: (to , the LSB) and .
- Q chooses which decoder is active (: outputs to ; : outputs to ), so Q is the MSB: .
- P gates both decoders together: when both are disabled and every output is 1; when the addressed output goes to 0. So the addressed output follows P, which makes P the data input: .
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