GATE EC 2016 Set 2 — Question 26
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Digital Circuits → Combinational Logic → Static CMOS Logic Gates
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Question
Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor . This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?
Correct answer
(B) Widths of PMOS transistors should be doubled, while widths of NMOS transistors should not be changed.
Solution
In a CMOS inverter, let the PMOS width be and NMOS width be . The charging resistance is and discharging resistance is . For a 2-input NOR gate:
1.Charging path (PMOS): Two PMOS transistors are in series. To maintain the same worst-case charging time (equivalent resistance), the total resistance must equal . If , then . Thus, PMOS widths should be doubled.
2.Discharging path (NMOS): Two NMOS transistors are in parallel. The worst-case discharge occurs when only one NMOS is ON. To match the inverter's discharge time, the resistance of a single NMOS must be . Thus, . NMOS widths should not be changed.
Therefore, option (B) is correct.Continue learning with Success Tracker
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